The present invention relates to a memory device, and more particularly a semiconductor memory device fabricated as an integrated circuit (hereinafter abbreviated as "IC").
In general, an access operation of a memory such as a read-only memory (hereinafter abbreviated as "ROM"), a random access memory (hereinafter abbreviated as "RAM") fabricated as an IC (memory IC) is controlled by a control processing unit (hereinafter abbreviated as "CPU") which controls a system including the memory IC's. In this respect, interfacing between memory IC's and CPU, has been a significant problem. Basically it is possible to match the interfacing provided that structures of addresses and data buses are coincident between the CPU and the memory IC's. However, in such cases, there still remains a problem in that the processing time required for a data read from a memory IC (hereinafter called "access time") is not identical to the duration of a read signal or a write signal from a CPU. The aforementioned access time is largely influenced by the memory capacity, an internal circuit structure of the memory IC. In recent years, large-capacity memories have been required in various application systems, hence there is a trend toward developing memory IC's having increased capacity. As the memory capacity is increased, the load capacitance of the memory is greatly increased, resulting in elongation of the access time.
In addition, in application systems employing batteries as a power supply, memory IC's consisting of complementary MOS device (hereinafter abbreviated as "CMOS") constructions operable with low power consumption are used in place of the heretofore known memory IC's consisting of n-channel MOS device (hereinafter abbreviated as "nMOS") constructions. Memory IC's of CMOS construction require long access time as compared to memory IC's of nMOS construction, although the former operate with low power consumption. In particular, in a CMOS ROM, in which a plurality of n-channel transistors as memory cells are connected in series for the purpose of enhancing the degree of integration, the access time of the ROM is determined by the number of the serially connected transistors performing as a time constant circuit, so that the access time of such CMOS type ROM is several-ten-fold longer as compared to the high-speed ROM's.
In the case of a memory IC having an access time equal to or shorter than that required by the CPU, the CPU can operate at its inherent speed. However, in the case of a memory IC having an access time longer than that required by the CPU, it is necessary to elongate the read signal and the write signal by extending the read cycle and the write cycle, respectively, of the CPU.
However, among the known methods, the method of slowing down the operation speed of a CPU has a shortcoming that the operation and processing speed of the entire application system is slowed down because the operation speed of the CPU is slowed down even at a time other than an access time of a memory IC.
In addition, in the case of utilizing a ready function, as above referred ready signal circuit, separate circuits are necessitated for respective memory IC's each having a different access time. There exists the disadvantage that the above-referred ready signal circuits are as many as the number of species of the access time of the memory IC's employed in the application system.
Moreover, in order that each of the above-referred ready signal circuits may operate only when a relevant memory IC has been selected, the respective ready signal circuits must be associated with a selection circuit such as an address decoder, and hence there is a disadvantage that the circuit construction becomes complex.
In recent years, construction of application systems has been made compact by making use of large-capacity memories, and even a handy type application system is manufactured in which a CPU, ROM, RAM, etc. are all formed of a CMOS structure. Accordingly, as application systems becomes more compact, it is desirable for the systems to have a smaller number of the mentioned additional circuits. Hence addition of the above-referred ready signal circuits as well as the aforementioned selection circuits, as is the case with the prior art, not only would prevent the application system from being made compact but also would result in a rise of the system cost, and this would be a big disadvantage.